Exploiting Multi-Level Parallelism For FPGA SoCs Using Polyhedral Model

dc.contributor.advisor	天野, 英晴 / 教授
dc.contributor.author	SIT, MAN KIT / 薛, 文傑
dc.date.accessioned	2018-11-16T03:56:46Z
dc.date.available	2018-11-16T03:56:46Z
dc.date.issued	2018-09-21
dc.description	修士（工学）, 2018, 開放環境科学専攻
dc.identifier.uri	/sigma_local/handle/10721/11316
dc.publisher	慶應義塾大学理工学研究科
dc.subject	並列処理	ja
dc.subject	FPGA	ja
dc.subject	多面体モデル	ja
dc.subject	Parallel computing	en
dc.subject	FPGA	en
dc.subject	Polyhedral model	en
dc.title	Exploiting Multi-Level Parallelism For FPGA SoCs Using Polyhedral Model
dc.title.alternative	Exploiting Multi-Level Parallelism For FPGA SoCs Using Polyhedral Model
dc.type	学位論文

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